The present invention relates generally to circuit layouts and more particularly to optimizing circuit layouts for analog and RF (radio frequency) circuits.
Circuit design for analog and RF circuits poses a number of unique challenges. In order for a circuit to perform correctly when manufactured using a semi-conductor process, several techniques have been employed when positioning devices (i.e., analog and RF devices) in the layout.
For example, a common technique involves matching the ratios of sizes, orientations and other properties between one or more devices in order to achieve electrical equivalence between these devices when manufactured. Additionally, in order to minimize the influence of process variations, certain groups of devices are placed in close proximity to each other. Another common matching technique involves positioning devices “symmetrically” by mirroring their orientations and usually aligning them in one dimension an equal distance from a specified symmetry line.
Analog and RF circuits often have several groups of devices, where each group must be individually arranged in proximity to one another as described above and where each group often requires local symmetry lines to position devices in symmetric arrangements within that group. Grouping of devices is also performed to isolate certain devices from other groups by surrounding them with a guard-ringed structure in the layout, or inserting them into a certain type of well in the semiconductor process. Once these devices are grouped, an additional requirement involves matching variations across these groups. This is accomplished by aligning the symmetry lines of these groups with respect to each other or by aligning the group boundaries with respect to each other. Sometimes, two or more devices that need to be matched very strongly may be combined into a single layout instance, often referred to as a “compound device.” These devices may be combined using user specified patterns to ensure perfect matching.
An additional objective when arranging these devices is to minimize the lengths of various connections between the devices in the circuit. These connections are often implemented using metal wires, and minimizing their lengths reduces the amount of space and material needed for implementation. Further, the resistances and capacitances introduced by these wires can adversely affect the electrical behavior of the circuit, and these effects need to be minimized as well. Certain connections in the circuit sometimes have more impact on the performance than other connections. It is therefore desirable to reduce lengths of specific paths or connections depending on the flow of currents and signals through the circuit. These signal and current paths are often identified by circuit designers who perform simulations of the electrical behavior of the circuit. This information is then either conveyed to a layout designer, who arranges the devices in the layout, or is used by the circuit designers themselves if they implement the layout on their own. An example involves identifying DC current paths through the circuit from the current source (often the positive voltage source, VDD) to the current sinks (often the negative voltage source, VSS, or the ground connection, GND). The devices in the layout are then arranged to minimize the lengths of wires connecting from the current sources to various devices and then to the current sinks.
While accounting for these various considerations, it is also necessary to meet several process design rule criteria for successful fabrication. An example is the restriction imposed on the minimum spacing between geometry on a given mask layer. This further imposes restrictions on the distances between various devices in the layout. Another objective is to minimize the total area occupied by all the devices, in order to minimize the mask costs during fabrication.
In some contexts, circuit layout design is discussed in terms of cell layout design, where a cell is a device arrangement that can be used as a building block for larger circuits. Then the area of a given cell may also be constrained by how this cell is packaged along with other cells when finishing the block-level layout. These constraints may be captured as restrictions on the height and/or width of the cell layout. Sometimes, the shape of the cell area may also be restricted to a certain rectilinear arrangement to fit with other cells. For example, the cell may be L-shaped instead of rectangular. Certain regions in the cell layout may also be designated as “keep-out” regions where one may not place any other devices. This latter construct is useful to reserve space for inserting other devices and/or geometry at a later point in the design cycle.
Currently most designers implement their semiconductor layouts manually for analog and RF circuits. Positioning the devices for matching, symmetry, grouping, minimizing area, wire-length, lengths of signal paths, etc., is performed by hand. Information regarding matching requirements, symmetry, critical signal and DC paths, observed from electrical simulations, is often annotated as text or graphics on the schematic by the designers. The layout designer then uses this information as a guideline when positioning these devices. At other times, for simplicity, the layout designer may position the devices as they are observed on the schematic, assuming that the positions of these devices on the schematic are an indication of the proximity of devices and optimal with regard to minimum lengths of critical signal or current paths. Another simple approach involves looking at previous implementations of the circuit, for example, a layout performed for a similar schematic, or a layout performed for a different set of device parameters for the same schematic, or a circuit implemented in a different semiconductor technology for the same or similar schematic. The layout designer then arranges the layout to look similar to the previous layout, with regard to the positioning of certain devices and/or groups of devices.
Some constraints like matching, symmetry and design rules, however, are very difficult to precisely implement by hand. Further, since there are a large number of possible arrangements of devices in a layout, it can be very difficult to analyze the impact of multiple tradeoffs between objectives like wire-length, area and lengths of signal paths manually. To address this, some conventional tools automate the generation of Analog and RF layouts by capturing these requirements as analytical constraints, possibly represented on a discrete grid for placing devices. Some of these approaches are described, for example, in analog design articles. (A. Shah, S Dugalleix and F Lemery, “High-performance CMOS-amplifier design uses front-to-back analog flow”, EDN design feature, Oct. 31, 2002.) However, these tools are typically limited in their ability to optimize performance features while imposing design constraints such as symmetry, matching and grouping. For example, a grid formulation may limit placement options such as the orientation of devices. Further, these tools are also typically limited in their ability to support “layout migration”, where a previously determined layout is taken as a starting point for a modified set of constraints or optimization criteria.
Thus, there is a need for improved methods and systems for optimizing circuit layouts, especially in applications involving analog and RF circuits.